The present invention relates to display controllers for digital display devices such as liquid crystal displays, plasma displays and progressive-scan televisions.
One commonly used type of display panel is a liquid crystal display (LCD) panel. An LCD display panel is a rectangular grid of rectangular or square dots. The grid includes transparent electrodes laid out in horizontal rows on one thin pane, and in vertical columns on the other. The liquid crystal formula trapped in between the panes reacts to an electrical field applied to each electrode in the rows and columns. This reaction rotates the polarization of light transmitted through the LCD display. Polarizing layers outside the panes cause the dots to appear light or dark as the polarization changes.
The display is controlled by continuously feeding dot data to the display. The data is organized into individual pixels, rows of pixels, and full-page frames. A set of rows makes up a frame, which is one full page of the display. LCD data is continuously sent to the LCD panel to refresh the display frame. Since most LCD displays have no on-board frame buffer memory, the display data must be continuously refreshed. To get a stable, flicker-free image, the display data is sent to the panel at a frame refresh rate (referred to herein as the “frame rate”) which falls within a range normally specified by the LCD panel manufacturer. An LCD panel manufacturer may specify, for example, that best results are obtained, i.e., a stable, flicker-free image, when the display data is sent to the panel 60 to 70 times per second, or 60 Hz to 70 Hz.
The LCD may be driven by different computers with different display resolutions. To insure the minimum level of interoperability between a digital flat panel (DFP) compliant monitor and host, both the monitor and host must support the video modes 640×400-60 Hz, 720×400-60 Hz, and 640×480-60 Hz. The DFP monitor must produce a viewable image with all of these video modes. The pixel clock for 640×400 and 720×400 shall be scaled down so the refresh rate is adjusted from 70 Hz to 60 Hz. The definition of a viewable image is all pixels are visible to the end user. Note that this does not mean that the monitor must support scaling or centering. It is considered acceptable for the image to be displayed in the upper left corner of the LCD. Monitors that have a native resolution of 640×480 are not required to fully display 720×400. If a DFP monitor is bundled with a DFP host or video card that does support scaling or centering, the monitor may rely on the host and is not required to provide this lower resolution support.
To illustrate, a VGA 640×480 pixel screen output can be displayed in a reduced area on a 1024×768 SVGA flat panel display. This type of display method would leave 384 pixels blank at the right of the screen and 288 blank lines at the bottom of the page. To increase the usable screen area, both horizontal and vertical expansion, preferably by the correct scale factor, are required. The image expanding can be done by replication of pixels horizontally or vertically or both. Typically, vertical lines may be added by periodically replicating the pixels of the preceding line to provide the desired expansion factor. However, horizontal expansion of character data is not provided because the character clock is typically used to clock the display, this being a submultiple of the pixel clock rate. Thus, the aspect ratio of text screens may be distorted by the vertical expansion without a corresponding horizontal expansion.
Another approach in flat panel technology replicates pixels vertically using the panel logic to simultaneously activate two row drivers at selected times. The column drivers are usually split into several chips and all of them must be driven simultaneously during one line scan, making it impossible to replicate pixels horizontally.
U.S. Pat. No. 5,600,347 discloses a system for horizontal expansion of low resolution display modes onto high resolution displays at a variable scaling factor. Two different methods are provided for graphics and text modes to attain better screen image quality. In the first method, a first pixel data sequence to be expanded is first oversampled at a multiple of the frequency thereof to produce an intermediate oversampled data sequence. The oversampled data sequence is linearly decimated by a factor of less than unity to produce a replicated second data sequence longer than the first, which is then displayed. In the second method, the intermediate oversampled data sequence is filtered to provide an interpolated oversampled data sequence, which is then decimated instead of the intermediate oversampled data sequence, to further improve the screen image quality.
U.S. Pat. No. 6,177,922 discloses a method and apparatus for producing video signal timing for a display device that has a display format different from the input video format. The system performs variable scale horizontal expansion of a first sequence of data elements to a second longer sequence of data elements for higher resolution display, in which the first data sequence is oversampled at a multiple of the frequency thereof, and then linearly decimated by a factor of less than unity to produce the second data sequence. The variable scale horizontal expansion is performed with a scaling factor (m/n). Horizontal expansion of a first sequence of data elements by a factor of two is performed, followed by horizontal compression by a factor of (m/2n). For example, a 640 pixel line may be expanded to 1024 pixels by first replicating every pixel to derive 1280 pixels, and then decimating the result by deleting (2n−m) pixels out of every 2n pixels. In operation with a typical computer graphics subsystem, the controller chip runs with its pixel clock rate divided by 2 and its output oversampled by a factor of 2. Then, selected pixel clock signals are deleted by the decimator logic. Although there are discontinuities in the pixel clock rate, the output pixels are compressed into the flat panel display because the data are first clocked into the display and then latched for a whole line period while the next line is assembled. Any screen compression ratio between 1 and 2 may thus be achieved by deleting the appropriate number of pixel clocks. Expansion by factors of more than 2 may also be achieved by increasing the oversampling ratio prior to decimation. When combined with vertical expansion methods, the system may be used to only perform expansion to any size of flat panel display from a lower resolution image.
Conventional image scaling controllers require their output clock to the LCD panel interface to match their input clock at a fixed rate to keep the frame rate equal between the input to each controller and the output to the LCD panel interface.
The '922 patent needs to generate a clock signal (“target clock signal”) which is synchronized with a reference clock signal. The two clock signals generally have unequal frequencies. For the purpose of illustration, the target clock signal may need to have a frequency of X/Y times the frequency of the reference clock signal, wherein X and Y are integers. To solve the above difficulty, the device in the '922 patent operates in conjunction with a rather complex method and apparatus for generating a target clock signal having a frequency of X/Y times the frequency of a reference clock signal, as discussed in a companion patent U.S. Pat. No. 6,157,376. The '376 patent discloses a clock generator circuit which provides for short comparison cycles even if X and Y do not have a large common denominator when a target clock signal having a frequency of (X/Y) times the frequency of a reference clock signal is to be generated. The comparison cycle is shortened by using approximately X/L and Y/L as divisors, instead of X and Y. As X/L and/or Y/L may not equal integers, multiple divisors may be used in a weighted fashion such that the weighted averages equal X/L or Y/L as the case may be.